Image sensors, such as Complementary Metal Oxide Semiconductor image sensors, output image signals from an array of pixels to column output circuits. FIG. 1 is a schematic diagram of a first column output circuit in accordance with the prior art. Each column of pixels in a pixel array 100 is electrically connected to a sample and hold circuit 102. For simplicity, only one sample and hold circuit is shown in FIG. 1. Capacitors 104 are each electrically connected to column output line 106 via switches 108. Each capacitor 104 is electrically connected to a respective local bus 110 through one of the switches 112 and eventually to a respective global bus 114 via one of the switches 116. Amplifiers 118 are connected to global buses 114 and receive the signals stored on capacitors 104.
When the accumulated charges are read out of pixel array 100, the reset signals for one row of pixels are typically simultaneously stored on one capacitor 104 in sample and hold circuit 102 and the image signals stored on the other capacitor 104. Reading out the stored charges on capacitors 108 is performed serially. To read out charge from capacitors 108 connected to column line 106, local busses 110 and global busses 114 are first pre-charged to a reference voltage to prevent “memory” effects from charge read out of a previous column. Then the appropriate switches in switches 112 and 116 are closed, and the stored capacitor charge is redistributed between the capacitors 108 and the parasitic capacitance of the global buses 114. The parasitic capacitances produced by the relatively long global busses, however, reduce the gain of the recovered signal. To compensate for this reduced gain, a gain is applied to the charge read out of amplifiers 118. The applied gain increases the noise level along with the signal level, an undesirable result because the noise degrades the quality of the captured image.
FIG. 2 is a schematic diagram of a second column output circuit in accordance with the prior art. Again, each column of pixels in a pixel array 200 is electrically connected to a sample and hold circuit 202. For simplicity, only one sample and hold circuit is shown in FIG. 2. Each sample and hold circuit 202 includes a pair of capacitors 204 each electrically connected to the pixel column bus 206 respectively via switches 208. Each capacitor 204 is electrically connected to a respective buffer amplifier 210 for storing the charge from capacitors 204 and for isolating the signal on the capacitors 204 from the local bus 212. The buffer amplifiers 210 are electrically connected to local bus 212 through switches 214 and eventually to the global bus 216 via switches 218.
The accumulated charges are read out of pixel array 200 using the same method described in conjunction with FIG. 1. The buffer amplifiers 210 in FIG. 2 are built at the same width as the width of a pixel column, which is typically very small. The very small size required for these buffers severely compromises their noise and speed performance, since it is well known that amplifier noise is inversely related to transistor size. The space required to instantiate 2*N buffers for an array of N pixels is another drawback to this approach.